1. Field of the Invention
The present invention relates to dynamic logic and domino logic functions, and more particularly to a P-domino output latch with an accelerated evaluate path.
2. Description of the Related Art
In recent years, domino circuits are being used more and more because of the speed advantages that they provide to an integrated circuit design. A typical domino output latch consists of three stages: 1) an evaluation stage in which an evaluation node is pre-charged to a specified state during one half of a clock cycle, and in which the state of the evaluation node is allowed to change during a second half of the clock cycle based upon the states of one or more inputs to function evaluation logic within the evaluation stage; 2) a latching stage that latches a representation of the evaluated state of the evaluation node at a latch node; and 3) a buffering or inverting stage that conditions the state of the latch node for distribution to subsequent logic as an output signal. Domino circuits are fast because the signal upon which the output signal is based (i.e., the state of the evaluation node) is already pre-charged (i.e., pre-set) to one logic level and because the function evaluation logic is comprised of only one type of logic devices, that is, either N-channel devices or P-channel devices. Speed benefits are gained in a domino circuit over conventional CMOS static logic because of reduced input capacitance, lower switching threshold levels, and the absence of parasitic diffusion capacitances on the outputs of the function evaluation logic. Designers are finding domino circuits particularly suitable for very high speed and time critical applications such as those found in the microprocessor and digital signal processing areas.
Speed improvements over conventional CMOS logic notwithstanding, the present inventors have observed that the data-to-output time of present day domino latch is the result of three levels of device delay (also known as “gate delay”): one level of delay through the evaluation stage, one level of delay through the latching stage, and a final level of delay through the buffering stage. In the context of a present day integrated circuit that is manufactured under a 90 nanometer fabrication process, each level of gate delay contributes approximately 15 to 20 picoseconds (ps), thus resulting in an overall data-to-output time of approximately 45 to 60 ps, which is roughly one-third of a clock cycle in a present day integrated circuit designed for high-end applications.
Consequently, it is desirable to provide a domino latch that provides all of the above noted benefits, but which has a reduced data-to-output time over that which has heretofore been provided.
It is also advantageous to provide a P-domino latch with an accelerated evaluation path for applications that are time critical.